PCF8811USLASH2DASLASH1 datasheet(51/73 Pages) PHILIPS

51 / 73 page

2004 May 17

Philips Semiconductors

Product speciﬁcation

× 128 pixels matrix LCD driver

PCF8811

Notes

1. All specified output timings are based on 20 % and 80 % of VDD1.

2. Cb = 100 pF total capacitance of one bus line.

tSU;STO

set-up time for STOP condition

160

−−

Cb2

capacitive load for the SDAH

and SCLH lines

note 2

−−

100

capacitive load for the

SDAH + SDA line and

SCLH + SCL line

note 2

−−

400

tSP

tolerable spike width on bus

−−

5ns

VnL

noise margin at the LOW-level

for each connected device

(including hysteresis)

0.1VDD1

−−

VnH

noise margin at the HIGH-level

for each connected device

(including hysteresis)

0.2VDD1

−−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

handbook, full pagewidth

MSC610

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDA

SCL

tBUF

tSP

tHD;STA

Fig.41 I2C-bus timing diagram (Fs-mode).

S = Start.

Sr = Start repeated.

P = Stop.

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