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C161PI Fiches technique(PDF) 15 Page - Infineon Technologies AG |
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C161PI Fiches technique(HTML) 15 Page - Infineon Technologies AG |
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15 / 82 page ![]() &3, Data Sheet 13 1999-07 Functional Description The architecture of the C161PI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161PI. Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section). Figure 4 Block Diagram (no internal ROM) Instr./Data 3(& &38 &RUH Interrupt Bus Internal RAM ÃF7r Port 2 Port 3 Port 4 Port 1 8 16 16 Data Data 32 Watchdog Port 5 6 C161RI V0.1 &38 &&RUH 16 External Instr./Data 16 USART ASC Sync. Channel (SPI) SSC XTAL 15 BRG BRG 16 Peripheral Data GPT 1 T 3 T 4 T 2 XRAM 2 KByte GPT 2 T 6 T 5 I²C-Bus Interface 16 Interrupt Controller 11 ext. IR OSC (input: 16MHz; prescaler or direct drive) External Bus (MUX only) & XBUS Control, CS Logic (4 CS) 16 8 7 4- Channel 8-bit ADC RTC Oscillator (16MHz) PLL 10-bit |
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