Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

Preview PDF HTML

C161PI Fiches technique(PDF) 78 Page - Infineon Technologies AG

No de pièce C161PI
Description  16-Bit Single-Chip Microcontroller
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  INFINEON [Infineon Technologies AG]
Site Internet  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C161PI Fiches technique(HTML) 78 Page - Infineon Technologies AG

Back Button C161PI Datasheet HTML 74Page - Infineon Technologies AG C161PI Datasheet HTML 75Page - Infineon Technologies AG C161PI Datasheet HTML 76Page - Infineon Technologies AG C161PI Datasheet HTML 77Page - Infineon Technologies AG C161PI Datasheet HTML 78Page - Infineon Technologies AG C161PI Datasheet HTML 79Page - Infineon Technologies AG C161PI Datasheet HTML 80Page - Infineon Technologies AG C161PI Datasheet HTML 81Page - Infineon Technologies AG C161PI Datasheet HTML 82Page - Infineon Technologies AG  
Zoom Inzoom in Zoom Outzoom out
 78 / 82 page
background image
&3,
Data Sheet
76
1999-07
Figure 24
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2)
The leading edge of the respective command depends on RW-delay.
3)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4)
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5)
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
W
37 in order to be safely synchronized. This is guaranteed,
if READY is removed in reponse to the command (see Note
4)).
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7)
The next external bus cycle may start here.
CLKOUT
ALE
W
30
W
34
Sync
READY
W
35
W
36
W
35
W
36
Async
READY
W
58
W
59
W
58
W
59
waitstate
READY
MUX/Tristate
6)
W
32
W
33
W
29
Running cycle
1)
W
31
W
37
3)
3)
5)
Command
RD, WR
W
60
4)
see 6)
2)
7)
3)
3)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82


Fiches technique Télécharger

Go To PDF Page


Lien URL



ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Lien vers la fiche technique    |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com