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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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C161PI Fiches technique(PDF) 11 Page - Infineon Technologies AG |
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C161PI Fiches technique(HTML) 11 Page - Infineon Technologies AG |
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11 / 82 page  &3, Data Sheet 9 1999-07 EA 35 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C161PI to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to ‘0’. PORT0 P0L.0-7 P0H.0-7 38- 45 48- 55 40- 47 50- 57 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of external bus configurations, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 - A15 AD8 - AD15 PORT1 P1L.0-7 P1H.0-7 56- 63 66- 73 58- 65 68- 75 IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Table 1 Pin Definitions and Functions (continued) Symbol Pin Num. TQFP Pin Num. MQFP Input Outp. Function |
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