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C161PI Fiches technique(PDF) 70 Page - Infineon Technologies AG

No de pièce C161PI
Description  16-Bit Single-Chip Microcontroller
PDF  82 Pages
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Fabricant  INFINEON [Infineon Technologies AG]
Site Internet  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C161PI Fiches technique(HTML) 70 Page - Infineon Technologies AG

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&3,
Data Sheet
68
1999-07
Data hold after WR
W
24
CC
15 +
W
F
–
TCL - 10
+
W
F
–ns
ALE rising edge after RD,
WR
W
26
CC
-12 +
W
F
–-12 +
W
F
–ns
Address hold after WR
2)
W
28
CC
0 +
W
F
–0 +
W
F
–ns
ALE falling edge to CS
3)
W
38
CC
-8 -
W
A
10 -
W
A
-8 -
W
A
10 -
W
A
ns
CS low to Valid Data In
3)
W
39
SR
–
47 +
W
C + 2WA
–
3TCL - 28
+
W
C + 2WA
ns
CS hold after RD, WR
3)
W
41
CC
9 +
W
F
–
TCL - 16
+
W
F
–ns
ALE falling edge to
RdCS, WrCS (with RW-
delay)
W
42
CC
19 +
W
A
–
TCL - 6
+
W
A
–ns
ALE falling edge to
RdCS, WrCS (no RW-
delay)
W
43
CC
-6 +
W
A
–-6
+
W
A
–ns
RdCS to Valid Data In
(with RW-delay)
W
46
SR
–
20 +
W
C
–
2TCL - 30
+
W
C
ns
RdCS to Valid Data In
(no RW-delay)
W
47
SR
–
45 +
W
C
–
3TCL - 30
+
W
C
ns
RdCS, WrCS Low Time
(with RW-delay)
W
48
CC
38 +
W
C
–
2TCL - 12
+
W
C
–ns
RdCS, WrCS Low Time
(no RW-delay)
W
49
CC
63 +
W
C
–
3TCL - 12
+
W
C
–ns
Data valid to WrCS
W
50
CC
28 +
W
C
–
2TCL - 22
+
W
C
–ns
Data hold after RdCS
W
51
SR
0
–
0–ns
Data float after RdCS
(with RW-delay)
1)
W
53
SR
–
30 +
W
F
–
2TCL - 20
+ 2
W
A + WF
1)
ns
Data float after RdCS
(no RW-delay)
1)
W
68
SR
–
5 +
W
F
–
TCL - 20
+ 2
W
A + WF
1)
ns
Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
W
A + WC + WF (100 ns at 20 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1 / 2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.



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