5M40ZE64C5N datasheet(27/30 Pages) ALTERA

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Chapter 3: DC and Switching Characteristics for MAX V Devices

3–27

Timing Model and Specifications

May 2011

Altera Corporation

MAX V Device Handbook

LVDS and RSDS Output Timing Specifications

Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.

Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices

Parameter

Mode

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z/5M1270Z/

5M2210Z

Unit

C4, C5, I5

Min

Max

Data rate (1), (2)

10

—

304

Mbps

9

—

304

Mbps

8

—

304

Mbps

7

—

304

Mbps

6

—

304

Mbps

5

—

304

Mbps

4

—

304

Mbps

3

—

304

Mbps

2

—

304

Mbps

1

—

304

Mbps

tDUTY

—45

Total jitter (3)

——

0.2

tRISE

——

450

tFALL

——

450

Notes to Table 3–39:

(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R

I/O buffer or 2x (FMAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through

the Quartus II timing analysis of the complete design.

(2) For the input clock pin to achieve 304 Mbps, use I/O standard with VCCIO of 2.5 V and above.

(3) This specification is based on external clean clock source.

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