3–12

Chapter 3: DC and Switching Characteristics for MAX V Devices

Timing Model and Specifications

MAX V Device Handbook

May 2011

Altera Corporation

Internal Timing Parameters

Internal timing parameters are specified on a speed grade basis independent of device

density. Table 3–18 through Table 3–25 on page 3–19 list the MAX V device internal

timing microparameters for LEs, input/output elements (IOEs), UFM blocks, and

MultiTrack interconnects.

AN629: Understanding Timing in Altera CPLDs.

UFM

512 × 16

None

3

1

10.0

10.0

10.0

10.0

MHz

512 × 16

SPI (2)

37

1

9.7

9.7

8.0

8.0

MHz

512 × 8

Parallel

(3)

73

1

(4)

(4)

(4)

(4)

MHz

512 × 16

142

1

100 (5)

100 (5)

100 (5)

100 (5)

kHz

Notes to Table 3–17:

(1) This design is a binary loadable up counter.

(2) This design is configured for read-only operation in Extended mode. Read and write ability increases the number of logic elements (LEs) used.

(3) This design is configured for read-only operation. Read and write ability increases the number of LEs used.

(4) This design is asynchronous.

Table 3–17. Device Performance for MAX V Devices (Part 2 of 2)

Resource

Used

Design Size and

Function

Resources Used

Performance

Unit

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

Mode

LEs

UFM

Blocks

C4

C5, I5

C4

C5, I5

Table 3–18. LE Internal Timing Microparameters for MAX V Devices (Part 1 of 2)

Symbol

Parameter

5M40Z/ 5M80Z/ 5M160Z/

5M240Z/ 5M570Z

5M1270Z/ 5M2210Z

Unit

C4

C5, I5

C4

C5, I5

Min

Max

Min

Max

Min

Max

Min

Max

LE combinational look-up

table (LUT) delay

—

1,215

—

2,247

—

742

—

914

ps

Combinational path delay

—

243

—

309

—

192

—

236

ps

LE register clear delay

401

—

545

—

309

—

381

—

ps

LE register preset delay

401

—

545

—

309

—

381

—

ps

LE register setup time

before clock

260

—

321

—

271

—

333

—

ps

LE register hold time

after clock

0

—0

—0

—0

—

ps

LE register

clock-to-output delay

—

380

—

494

—

305

—

376

ps