ST72C171 datasheet(51/152 Pages) STMICROELECTRONICS

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ST72C171

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7.5 16-BIT TIMER

7.5.1 Introduction

The timer consists of a 16-bit free-running counter

driven by a programmable prescaler.

It may be used for a variety of purposes, including

measuring the pulse lengths of up to two input sig-

nals (

input capture) or generating up to two output

waveforms (

output compare and PWM).

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Some ST7 devices have two on-chip 16-bit timers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modified.

This description covers one or two 16-bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

7.5.2 Main Features

Programmable prescaler: f

CPU divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times

slower than the CPU clock speed) with the choice

of active edge

Output compare functions with:

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Input capture functions with:

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

Pulse Width Modulation mode (PWM)

One Pulse mode

5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 1.

*Note: Some timer pins may not be available (not

bonded) in some ST7 devices. Refer to the device

pin out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

7.5.3 Functional Description

7.5.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

– Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register (SR).

(See note at the end of paragraph titled 16-bit read

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh (this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 1. The

value in the counter register repeats every

131.072, 262.144 or 524.288 CPU clock cycles

depending on the CC[1:0] bits.

The timer frequency can be fCPU/2, fCPU/4, fCPU/8

or an external frequency.

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