ST72C171 datasheet(86/152 Pages) STMICROELECTRONICS

86 / 152 page

ST72C171

86/152

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: Undefined

Bit 7 = R8

Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 5 = Reserved, forced by hardware to 0.

Bit 4 = M

Word length.

This bit determines the data length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is

set or cleared by software.

0: Idle Line

1: Address Mark

Bit 2:0 = Reserved, forced by hardware to 0.

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00 h)

Bit 7 = TIE

Transmitter interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SR register.

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SR register

Bit 5 = RIE

Receiver interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter and assigns the

TDO pin to the alternate function. It is set and

cleared by software.

0: Transmitter is disabled, the TDO pin is back to

the I/O port configuration.

1: Transmitter is enabled

Note: During transmission, a “0” pulse on the TE

bit (“0” followed by “1”) sends a preamble after the

current word.

Bit 2 = RE

Receiver enable.

This bit enables the receiver. It is set and cleared

by software.

0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of the SR register.

1: Receiver is enabled and begins searching for a

start bit.

Bit 1 = RWU

Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake-up sequence is

recognized.

0: Receiver in active mode

1: Receiver in mute mode

Bit 0 = SBK

Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

WAKE

TIE

TCIE

RIE

ILIE

RWU

SBK

ST72C171 Fiches technique(PDF) 86 Page - STMicroelectronics

ST72C171 Fiches technique(HTML) 86 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL