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ST72C171 Fiches technique(PDF) 32 Page - STMicroelectronics |
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ST72C171 Fiches technique(HTML) 32 Page - STMicroelectronics |
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32 / 152 page ![]() ST72C171 32/152 I/O PORTS (Cont’d) Figure 26 . I/O Block Diagram Table 5. Port Mode Configuration Legend: 0 - present, not activated 1 - present and activated Notes: – No OR Register on some ports (see register map). – ADC Switch on ports with analog alternate functions. DR DDR LATCH LATCH DR SEL DDR SEL VDD PAD ANALOG SWITCH ANALOG ENABLE (ADC) M U X ALTERNATE ALTERNATE ALTERNATE ENABLE ALTERNATE M U X ALTERNATE INPUT PULL-UP (SEE TABLE BELOW) OUTPUT P-BUFFER (SEE TABLE BELOW) N-BUFFER 1 0 1 0 OR LATCH OR SEL FROM OTHER BITS EXTERNAL PULL-UP CONDITION ENABLE ENABLE GND (SEE TABLE BELOW) (SEE NOTE BELOW) CMOS SCHMITT TRIGGER SOURCE (EIx) INTERRUPT SENSITIVITY SEL Configuration Mode Pull-up P-buffer Floating 0 0 Pull-up 1 0 Push-pull 0 1 True Open Drain not present not present Open Drain (logic level) 0 0 |
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