ST72C171 datasheet(70/152 Pages) STMICROELECTRONICS

70 / 152 page

ST72C171

70/152

PWM AUTO-RELOAD TIMER (Cont’d)

7.6.2 Functional Description

Counter

The free running 8-bit counter is fed by the output

of the prescaler, and is incremented on every ris-

ing edge of the clock signal.

It is possible to read or write the contents of the

counter on the fly by reading or writing the Counter

Access register (CAR).

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the

ARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

fCOUNTER = fINPUT / 2

CC[2:0]

The timer counter’s input clock (fINPUT) feeds the

7-bit programmable prescaler, which selects one

of the 8 available taps of the prescaler, as defined

by CC[2:0] bits in the Control/Status Register

(CSR). Thus the division factor of the prescaler

can be set to 2n (where n = 0, 1,..7).

This fINPUT frequency source is selected through

the EXCL bit of the CSR register and can be either

the fCPU or an external input frequency fEXT.

The clock input to the counter is enabled by the

TCE (Timer Counter Enable) bit in the CSR regis-

ter. When TCE is reset, the counter is stopped and

the prescaler and counter contents are frozen.

When TCE is set, the counter runs at the rate of

the selected clock source.

Counter and Prescaler Initialization

After RESET, the counter and the prescaler are

cleared and fINPUT = fCPU.

The counter can be initialized by:

– Writing to the ARR register and then setting the

FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the CSR register.

– Writing to the CAR counter access register,

In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.

Direct access to the prescaler is not possible.

Output compare control

The timer compare function is based on four differ-

ent comparisons with the counter (one for each

PWMx output). Each comparison is made be-

tween the counter value and an output compare

be accessed directly, it is loaded from the duty cy-

cle register (DCRx) at each overflow of the coun-

ter.

This double buffering method avoids glitch gener-

ation when changing the duty cycle on the fly.

Figure 42. Output compare control

COUNTER

FDh

FEh

FFh

FDh

FEh

FFh

FDh

FEh

ARR=FDh

fCOUNTER

OCRx

DCRx

FDh

FEh

FDh

FEh

FFh

PWMx

ST72C171 Fiches technique(PDF) 70 Page - STMicroelectronics

ST72C171 Fiches technique(HTML) 70 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL