ST72C171 datasheet(34/152 Pages) STMICROELECTRONICS

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ST72C171

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I/O PORTS (Cont’d)

7.1.3 Register Description

DATA REGISTERS

Port A Data Register (PADR)

Port B Data Register (PBDR)

Port C Data Register (PCDR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0]

Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

DATA DIRECTION REGISTERS

Port A Data Direction Register (PADDR)

Port B Data Direction Register (PBDDR)

Port C Data Direction Register (PCDDR)

Read/Write

Reset Value: 0000 0000 (00h) (input mode)

Bit 7:0 = DD[7:0]

Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bits is set and

cleared by software.

0: Input mode

1: Output mode

OPTION REGISTERS

PORT A Option Register (PAOR)

PORT B Option Register (PBOR)

PORT C Option Register (PCOR)

Read/Write

Reset Value: 0000 0000 (00h) (no interrupt)

Bit 7:0 = O[7:0]

Option Register 8 bits.

The PAOR, PBOR and PCOR registers are used

to select pull-up or floating configuration in input

mode.

Each bit is set and cleared by software.

Input mode:

0: Floating input

1: Input pull-up (with or without interrupt see Table

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

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