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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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VR4102 Fiches technique(PDF) 99 Page - NEC |
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VR4102 Fiches technique(HTML) 99 Page - NEC |
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99 / 701 page  99 CHAPTER 4 VR4102 PIPELINE This chapter describes the basic operation of the VR4102 processor pipeline, which includes descriptions of the delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused by interlocks and exceptions, and CP0 hazards. 4.1 PIPELINE STAGES The VR4102 has a five-stage instruction pipeline; each stage takes one PCycle (one cycle of Pclock), and each PCycle has two phases: )1 and )2, as shown in Figure 4-1. Thus, the execution of each instruction takes at least 5 PCycles. An instruction can take longer - for example, if the required data is not in the cache, the data must be retrieved from main memory. Once the pipeline has been filled, five instructions are executed simultaneously. Figure 4-1. Pipeline Stages Cycle Phase PCycle PClock IF )2 )1 )2 )1 )2 )1 )2 )1 )2 )1 RF EX DC WB The five pipeline stages are: — IF - Instruction cache fetch — RF - Register fetch — EX - Execution — DC - Data cache fetch — WB - Write back Figure 4-2 shows the five stages of the instruction pipeline. In this figure, a row indicates the execution process of each instruction, and a column indicates the processes executed simultaneously. |
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