ACE9030MSLASHIWSLASHFP2Q datasheet(30/39 Pages) MITEL

30 / 39 page

ACE9030

The reference divider needs to produce the main com-

parison frequency of 12·5 kHz from the crystal at 14·85 MHz,

a ratio of 1188, which can be formed by a NR of 1188 followed

by a SM select giving

÷1, or 594 followed by ÷2, or by 297 and

÷4. The auxiliary divider must divide 90 MHz down to the

auxiliary comparison frequency, which is related to the main

comparison frequency but can usefully be larger. Using

12·5 kHz needs a ratio of 7200 which is too large a value for

NA, 25 kHz needs 3600 and could be used, but 50 kHz and a

ratio of 1800 helps to minimise loop filter size. With this choice

the values to be set are:

NR = 297, to give 50 kHz into SA, SM selector.

SA = 00, to give

÷1, and leave 50 kHz for auxiliary

comparison frequency.

SM = 01, to give

÷4, and hence 12·5 kHz for main

compari

son frequency.

NA = 1800, to give 90 MHz.

In this example Fractional-N operation is not chosen, but if it

is required then SM should be set to 00 to give 50 kHz

comparison frequency in both synthesisers and then fractions

of 1/

4 or

4 used by setting NF = 2 or 6, with FMOD set to 1 to

give 1/

8’s. The values of N1 and N2 can then be found by

following a procedure similar to the following.

For the main synthesiser, starting at channel 1, to divide

980·0125 MHz down to 12·5 kHz is a total ratio of 78401 and

this will be split between the prescaler and the ACE9030

programmable divider. A

÷64/65 prescaler is most common,

and will be in

÷64 mode as its normal state, so the 78401 can

be split into a

÷64 followed by ÷1225 with a remainder of 1. The

remainder is achieved by setting the prescaler to

÷65 for 1

cycle, so using R1 = 64, and R2 = 65 the programmable values

can be:

N2 = 1, and (N1 + N2) = 1225, thus N1 = 1224

These values are suitable for use but are not the only

possible set - if desired N2 can be increased to 65 if N1 is

reduced to 1160. The actual choice in practice is set by

whichever gives the more convenient mathematics in the

system controller, the only limits are the basic equation:

TOT = (N1 + N2) x R1 + N2, which must be met for all channels

and the fact that a set value of 0 for N2 will actually give a count

of 256 so for easy calculations N2

 0 (in practice for a TACS

system not using Fractional-N all N2 values are odd numbers

so 0 is never needed).

Other channels can easily be added, without forgetting

that each channel is two comparison steps (2 x 12·5 kHz)

above the next lower, so for channels 1 to 32,

N2 = 2 x Channel Number – 1, and N1 = 1225 – N2

and for channels 33 to 64,

N2 = 2

∞ ( Channel Number – 32 ) – 1, and N1 = 1226 – N2

Rather than having several sets of separate equations for

each group of channels it is possible to combine them all into

one set by adding two variables to split the channel number

into a modulo-32 and a remainder number. Let C32 =

int((Channel Number – 1)

÷ 32), where “int(x)” means the

integer part of (x), and let CN2 = Channel Number – (32 x C32),

then:

N2 = (2 x CN2) –1, and N1 = 1225 – N2 + C32

These are clearly valid for channels 1 to 600 (the original

TACS channels) but to cover the extra channels for ETACS

the negative numbers need more processing to avoid nega-

tive N2 values. The simplest answer is to add an offset to the

channel number and then subtract an equivalent value from

the N1 equation. As the channels are in blocks of 32 for the

calculations it is helpful to choose a multiple of 32 for the offset,

and the most negative channel is –719 so the lowest suitable

offset value is 736 (that is 23 x 32). This gives the following

steps for all TACS/ETACS channels:

CNOFF = Channel Number + 736

CB32 = int((CNOFF – 1)

÷ 32)

CN2 = CNOFF – (32 x CB32)

N2 = (2 x CN2) – 1

N1 = 1202 – N2 + CB32

These operations are given in easy to understand stages

but in a real system it could be more efficient to combine or

rearrange some steps. If a high level language is used then

integer and remainder functions might be available and could

save a little programming time, whereas if low level or assem-

bler language is used an integer function will need to be built,

in this case by a 5 bit right shift to both divide by 32 and to lose

the fraction.

It might be noticed that avoiding N2 = 0 was very easy as

all values of N2 in this system are odd numbers, due to the 12·5

kHz offset from band edges. Other systems do not have this

offset so a little care is needed in choosing constants in the

corresponding equations.

DETAILED OPERATION OF FRACTIONAL-N MODE

Without using the Fractional-N mode the loop will lock the

VCO frequency, f

VCO to the comparison frequency, fCOMP at a

multiple set by the total division ratio N

TOT, where:

TOT = (N1 + N2) x R1 + N2

giving:

VCO = fCOMP x NTOT

From these equations it can be seen that if N

TOT is an

integer the minimum frequency step is f

COMP. It is not possible

to make a non-integer divider but by alternating the ratio

between N

TOT and NTOT + 1 in a suitable pattern the effect of a

fractional increase in N

TOT can be achieved. This is called

Fractional-N operation.

The control of the pattern of N

TOT and NTOT + 1 cycles is by

an accumulator set to count with a modulus equal to the

fractional denominator and which adds the numerator of the

fraction every comparison cycle. When the accumulator over-

flows by its value exceeding the value of the denominator the

total division ratio is increased for one cycle. In ACE9030 the

choice of denominator is 5 or 8 and is set by the FMOD bit in

Word D, the numerator is set by the three NF bits in Word A or

A2 and the increase in total division from N

TOT to NTOT + 1 is

done by changing the modulus control signal to the prescaler

so that an R1 cycle becomes an R1 + 1 cycle.

As an example of the operation of the accumulator

consider FMOD set HIGH to give modulo-8 counting and NF

set to 011 to give a 3/8 fraction and the accumulator starting at

any arbitrary value as shown in table 7.

From this table it can be seen that the pattern repeats every

8 cycles and that the ratio is incremented for 3 of each 8, giving

the desired N

TOT +

8. It can be shown that the pattern always

repeats every 8 cycles, or whatever modulus is chosen for all

fractions and that the number of N

TOT + 1 cycles is always the

fractional numerator.

By spreading the (N

TOT + 1) counts throughout the pattern

rather than having them as a continuous block the loop is less

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