ACE9030MSLASHIWSLASHFP2Q datasheet(14/39 Pages) MITEL

14 / 39 page

ACE9030

Data is accepted by the circuit on the rising edge of

LATCHC. Programmable divider ratios will be changed at their

next re-load, at up to a whole comparison period after the

LATCHC edge.

Normal channel changes require only word A but if it is

necessary to maintain exactly uniform loop dynamics the

parameter CN (see Main Synthesiser - Normal Mode) must

also change. This can be achieved by either sending a word

B for the CN parameter before word A for the frequency or

alternatively the extended command A2 can be used to

combine both in one long word. This A2 mode is not supported

by the ACE9050 as it is not necessary for most cellular

terminals.

If Word B is reprogrammed, the new values do not

become effective until the next Word A is written.

This

prevents any spurious conditions during a channel change.

The LG bit in Word D sets whether A or A2 mode is to be

used, 0 for A and 1 for A2.

Speed-up drive is active for the duration of the LATCHC

pulse that loads the A or A2 word and if it is required the pulse

will typically be hundreds of cycles of CL in duration.

In some applications the system performance can be

improved by holding LATCHC at HIGH to minimise clock noise

on the synthesisers. LATCHC also controls Speed-up mode

and so to exit speed-up mode after a channel change the

LATCHC must be driven LOW and then a dummy command

can be added to get LATCHC back to HIGH. This dummy

command should be a non-functional word formed by setting

the last four bits to 1111 as in figure 11; the value or the number

of the data bits before the four 1’s are of no significance so the

typical schemes are to send either a standard 24 bit message

ending 1111 or a special 4 bit only message of 1111 and in

both cases the LATCHC is kept HIGH until the next channel

change.

The TEST bits in Word B must be set to 0000 for normal

operation and the first two bits in Word B should be set to 00

to be sure of compatibility with future variants.

Summary of Synthesiser Programming

BIT STRING

Range of values

FUNCTION

3 - 4095

Main synthesiser down count; prescaler at lower modulus.

1 - 255

Main synthesiser up count; prescaler at higher modulus.

0 - 7

Main synthesiser fractional increment numerator.

TEST

0000

This state must be selected in every Word B for normal operation.

TEST pin will be held LOW to screen adjacent PDA pin.

Other test modes are for use during chip manufacture only.

0 - 255

Main charge pump current scaling coefficient.

0 - 15

Integral charge pump speed-up mode multiplying factor.

0 - 3

Proportional charge pump speed-up mode exponent, giving x 2, x4, x 8

or x 16 current.

3 - 4095

Auxiliary synthesiser VCO divider ratio.

8 - 4095

Reference divider ratio.

0 - 3

Main synthesiser comparison frequency select.

0, 1

Main synthesiser in standby mode if DM set HIGH.

0 - 3

Auxiliary synthesiser comparison frequency select.

0, 1

Auxiliary synthesiser in standby mode if DA set HIGH.

FMOD

0, 1

Fractional-N denominator, 1/5’s when at “0” or

8’s when at “1”.

0, 1

Control bus mode select - Word A if LOW or Word A2 if HIGH.

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