ACE9030MSLASHIWSLASHFP2Q datasheet(26/39 Pages) MITEL

26 / 39 page

ACE9030

Fractional-N mode

When selected this mode is permanently active and by

interpolating channels between comparison frequency steps

allows a higher comparison frequency to give both a faster

channel change time and a lower comparison sideband level.

The higher comparison frequency also allows a higher loop

bandwidth which can reduce phase noise in the locked sys-

tem. It is not difficult to get the Fractional-N loop compensation

correct to minimise sidebands at the fractional frequency as

Fig. 24 Main Synthesiser - Normal Mode

Main Synthesiser - Normal Mode

In Normal mode the Main synthesiser is similar to the

Auxiliary synthesiser with the addition of control for an external

prescaler, see figure 24.

The 12-bit counter first counts down for N1 cycles, with

MODMP set HIGH, then counts up for N2 cycles, with MODMP

set LOW, and finally gives an output pulse (every N1 + N2

cycles) to the phase comparator and repeats the whole

sequence. The use of an up/down counter allows the control

of a two modulus prescaler without needing a separate

counter for that purpose. To give time for the function

sequencing a minimum limit of 3 is put on N1 and a pro-

grammed value of 0 for N2 will be treated as 256 and so is not

normally used. Choices of values for N1 and N2 are described

in the later sections “Two Modulus Prescaler Control” and

“Programming Example for Both Synthesisers”.

The phase detector operates with the same arrangement

of overlapping up and down pulses as the Auxiliary phase

detector to again avoid any dead band, the charge pump

current is also set by the same resistor on pin RSMA but for the

Main charge pumps the current is also controlled by the bus.

In the bias circuit the current I

RSMA through the external resistor

on pin RSMA is divided by 32 to give a reference current Ibo

( Ibo = I

RSMA x

32 ) and this current is then multiplied by the

value CN from the control bus to give the normal charge pump

current Iprop(0). The pin RSMA again does not need any

decoupling and to avoid all possibilities of oscillation the

external capacitance should be less than 5 pF.

CN can be changed for different channels, to track the

division ratio set by N1 and N2, to maintain the same PLL loop

gain over the operating band but in most cellular systems the

total band is narrow compared to the frequencies and a fixed

CN is adequate. Other synthesiser control parameters do not

need changing and could be loaded at power-on and then left

unaltered.

Main Synthesiser - Normal Mode withSpeed-up

During Speed-up the drive to the loop filter is increased to

change channels faster. There will be a slight degradation of

sideband performance during the change but this does not

affect the final system performance. Speed-up lasts for the

duration of the LATCHC pulse that loads an A or A2 word from

the bus and as soon as the pulse ends the currents return to

normal to give clean synthesis. The normal charge pump

current is increased by a factor (2L+1) to give 2, 4, 8, or 16 times

Iprop(0), as defined in Normal Mode, and is then referred to as

Iprop(1), as in figure 26. A second charge pump is enabled to

drive the capacitor Ci in the loop filter directly, and as this is

always larger than capacitor Cp this extra output is set to

Iprop(1) x K. The factors L and K are used to control speed-up

and are loaded at power-up and can be left at fixed values.

Speed-up is always enabled by LATCHC when an A or A2

word is loaded. When speed-up is not required the LATCHC

pulse should be short and the parameters L and K set to their

minimum to give an insignificant effect.

Main Synthesiser - Fractional-N Mode

Fractional-N mode is the same as Normal mode with the

addition of the Fractional-N system, shown in figure 25.

In Fractional-N mode the modulus of the prescaler is

changed in a cyclic manner to interpolate channels between

the comparison frequency steps. Depending on the state of

the FMOD bit loaded in Word D the pattern can be 5

(FMOD = 0) or 8 (FMOD = 1) cycles long, giving the choice of

5’s or

8’s of the comparison frequency and the fractional

numerator is set by NF in Word A or A2. The accumulator

repeatedly adds NF to its own value and generates an

overflow whenever this value exceeds the count modulo

number. This overflow output to the Modulus Control logic will

force one cycle to change from MODMP HIGH to MODMP

LOW to in turn set the prescaler to the higher ratio for one cycle

the ACE9030 fractions are only 1/

5’s or

8’s. For further details

see the later section “Detailed Operation of Fractional-N

Mode”.

Fractional-N Mode with Speed-up

This gives the ultimate loop performance from the

ACE9030 but care is needed when designing the loop filter

and when choosing the values of the control parameters.

N1 & N2

FROM BUS

PHASE

DETECTOR

DOWN

12 BIT DOWN/UP

COUNTER

RESET

CHARGE

PUMP

PDP

MAIN COMPARISON

FREQUENCY (FROM

REFERENCE DIVIDER)

FIM

FIMB

MODMP

MODMN

MODULUS CONTROL

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