ACE9030MSLASHIWSLASHFP2Q datasheet(24/39 Pages) MITEL

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ACE9030

Main

bit 1 bit 0

Tap

÷1

÷4

÷2

÷8

FUNCTIONAL DESCRIPTION - BLOCKS IN THE SYNTHESISERS

There are two synthesisers in the ACE9030 for use by the

radio system, a Main loop to set the first local oscillator to the

frequency needed for the channel to be received and an

Auxiliary loop to generate an offset frequency to be mixed with

the Main output to give the transmit frequency. The modula-

tion is added to the Auxiliary loop by pulling the VCO tank

circuit and is then mixed onto the final carrier frequency. In a

typical cellular terminal the first Intermediate Frequency is

45 MHz so the Main synthesiser will be set 45 MHz above the

receive channel frequency. Many cellular systems operating

around 900 MHz use a 45 MHz transmit-receive offset, with

the mobile transmit channel below the receive channel fre-

quency so the Auxiliary synthesiser will be set to a fixed

frequency of 90 MHz.

Loop dynamics needed for the Main synthesiser are set

by the re-tuning time during hand-off and to help simplify the

off-chip loop filter components there are Fractional-N and

Speed-up modes available for this synthsiser, primarily for use

in ETACS terminals. The Auxiliary loop does not change

frequency so the only constraints are power-up time and

microphonics, so a simple synthesiser is used.

The two loops share a common reference divider to save

power and also to control the relative phase of the two sets of

charge pumps.

As described in the section FUNCTIONAL DESCRIP-

TION - CONTROL BUS there is often benefit in holding

LATCHC at a high level to minimise bus clock interference to

the synthesiser loops. The dummy word in figure 11 is the

preferred technique to set LATCHC to high for normal opera-

tion.

At power-on, the reset generator in the Radio Interface

section is used to initialise both synthesisers to their power

down state. In this state they can be programmed with

required numbers to be ready for power-on when the whole

terminal has fully initialised.

Fig. 22 Reference Divider

A common reference divider is used for the two synthesis-

ers, but to allow some difference in comparison frequencies

the final four stage output selectors are repeated for each

synthesiser as shown in figure 22. To reduce interaction

between the two synthesisers the divider outputs are ar-

ranged in antiphase so that loop correction charge pump

pulses occur alternately in each loop. This phase separation

also reduces the peak current in the charge pump power

supply and can reduce interference to other sections of the

mobile terminal.

The input clock to the reference divider is the internal

signal XO from the crystal oscillator. The two outputs drive the

Auxiliary and the Main phase detectors directly.

A standby mode is available for the reference divider and

is enabled whenever both synthesisers are in standby.

The programming numbers are all loaded from the serial

bus in Word D, NR directly sets the ratio of the 12 bit divider

but SA and SM select the final divisions as in the following

tables:

Auxiliary

bit 1

bit 0

Tap

÷1

÷4

÷2

÷8

The minimum allowed value of NR is set by the need to

generate some small time windows around the comparison

edges for Lock Detect logic and for Fractional-N compensation

so a value of at least 8 is required. The maximum NR is 4095

as normal for a 12 bit counter and this is then increased by a

factor of 1, 2, 4, or 8 in the final divider. A typical required

reference division is

÷512 so neither of these limits should

constrain the system design.

Reference Divider

SELECT

- 1/2/4/8

SELECT

12 BIT DIVIDER

NR FROM BUS

SM FROM BUS

COMP.FREQ.

TO AUXILIARY

PHASE DETECTOR

COMP.FREQ.

TO MAIN

PHASE DETECTOR

ACE9030M/IW/FP2Q Fiches technique(PDF) 24 Page - Mitel Networks Corporation

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