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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ACE9030M/IW/FP2Q Fiches technique(PDF) 17 Page - Mitel Networks Corporation |
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ACE9030M/IW/FP2Q Fiches technique(HTML) 17 Page - Mitel Networks Corporation |
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17 / 39 page  ACE9030 17 The ADC data in the five registers is read in response to a Normal command, with the two results to be output being selected by two bits of DATA3: DATA1 DATA2 DATA3 xxxxxxxx 01xxxxxx xxxxxxY 1Y0 where Y 1 Y0 are decoded to select: Y 1 Y 0 Data requested 0 0 ADC5 & ADC1 0 1 ADC5 & ADC2A/B 1 0 ADC5 & ADC3A/B 1 1 ADC5 & ADC4 The requested data is then clocked out after a fixed delay, with a preamble followed by the two results: PREAMBLE RESULT 1 RESULT 2 1010 Y 1 Y0 0 L RRRRRRRR RRRRRRRR The Y 1 Y0 code is output to confirm the data selection and is the same as in the Normal command that requested the data, detailed above, L is the Lock Detect status from the Lock Detect Filter, and the two results are in the order ADC5 in RESULT 1 and ADC1, 2, 3, or 4 in RESULT 2. The level in the ADC1 register is continuously compared with a threshold number such that if ADC1 is above this threshold the output pin RXCD is driven HIGH and can be used to indicate the presence of a received carrier. The threshold is set by a Normal command on the bus, with the value in DATA1: IREF Bias Circuit To set the operating current for several blocks in the Radio Interface there is a bias pin I REF which should be connected to the ground plane (V SS pins) via a resistor whose value de- pends on the supply voltage, 68 or 100 k Ω for 3·75 V or 4·85 V nominal V DD. The current into this pin is then mirrored to the various functional blocks. To reduce the noise on this bias a capacitor can be added from the IREF pin preferably to the supply or alternatively to a good ground. A value of 82 nF offers a good compromise between noise rejection and power-up time. D to A Converters There are three 8-bit DAC’s with buffered outputs in the ACE9030. DAC1 and DAC2 have a high zero offset, a nominally 15 k Ω output series resistor, and are stable when driving up to a 100 nF load capacitance. DAC3 has a low zero offset and no output resistor. In order to guarantee stability the capacitance of the load on DAC3 must be no more than 30 pF. The output resistors on DAC1 and DAC2 are used to form part of a low pass filter and these DAC’s are intended to be used to adjust the crystal frequency as given below under Crystal Oscillator. DATA1 DATA2 DATA3 DDDDDDDD 01xxxx D 1 x xxxx D 3 D2 xx DATA1 DATA2 DATA3 xxxxxxxx 01xx D 3 xxx xxxxxxxx The level for each DAC is set by a Normal command: where the data in DATA1 is loaded into DAC1 if DATA3 bit D 3 is HIGH, into DAC2 if DATA3 bit D 2 is HIGH, or into DAC3 if DATA2 bit D 1 is HIGH. DAC1 and DAC2 remain active during Sleep mode but the outputs are driven with reduced current capability; this will slightly reduce the accuracy and will significantly increase the settling time to any level change. DAC3 is powered down in Sleep mode. To power down DAC3 outside of Sleep mode, a Normal command may be used: where DAC3 is active if DATA2 bit D 3 is HIGH or powered down if DATA2 bit D 3 is LOW. L.F. Amplifiers Two identical low frequency amplifiers are provided; one has inputs AMPP1 and AMPN1 driving output AMPO1, the other has inputs AMPP2 and AMPN2 driving output AMPO2. A typical use for AMP1 is as a linear amplifier to buffer the DAC3 output to drive the transmit power control in a software controlled loop with a power sensor input to ADC5. AMP2 is typically used as a comparator to detect transmit power independent of the software as a system integrity check. The System Controller can then gate the presence of transmitter power on AMPO2 with the absence of received carrier on RXCD to detect a non-valid status and re-initialise the system. Crystal Oscillator A crystal oscillator maintaining circuit is provided on pins CIN1 and CIN2 for use with a crystal at 12·8, 14·85 or 15·36 MHz depending on the cellular system chosen. The circuit is designed for a crystal cut for a 20 pF load and with an ESR less than 25 Ω. To ensure reliable fast start times for this oscillator the bias current is increased significantly for the first 2047 cycles of oscillation after power-up, a restart command or after an oscillator ON command and then automatically changes to the lower normal level. The normal level has been chosen to still guarantee start-up if the circuit should be stopped by some external interference but to consume less power than the fast start mode. The buffered internal output of this oscillator is used in several sections of the chip and is referred to as XO in this data sheet. This oscillator can be trimmed by using DAC1 and DAC2 to control varicap diodes and so to pull the frequency, the two DAC’s may be used to give separate AFC and temperature compensation. A typical external circuit is shown in figure 14. Each DAC provides typically 30ppm tuning range. If preferred, an external oscillator can be used by driving into CIN1 with CIN2 left open circuit. To allow this external drive the internal oscillator should be shut down by using a Set-up command with DATA3 bit D 7 at LOW. The internal oscillator is switched on at power-up, at restart, and by a Set- up command with DATA3 bit D 7 at HIGH: DATA1 DATA2 DATA3 DDDDDDDD 01xxxxxx xxx1xxxx DATA1 DATA2 DATA3 xxxxxxxx 10xxxxxx D 7 xxxxx00 |
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