ACE9030MSLASHIWSLASHFP2Q datasheet(15/39 Pages) MITEL

15 / 39 page

ACE9030

FUNCTIONAL DESCRIPTION - BLOCKS IN THE RADIO INTERFACE

Power-On Reset Generator

To ensure a tidy start-up there is an internal power-on

detector to initialise various registers.

This initialisation leaves the Radio Interface in Sleep

mode with the crystal and 8·064 MHz oscillators running. The

8·064 MHz PLL will be set up for a 15·36 MHz crystal as a

default to ensure the microprocessor is not clocked too fast

during the start up sequence. Any Normal command can be

used to change to active operation.

A software Restart command can be sent to force the

Radio Interface to the power-on reset state. This command is:

DATA1

DATA2

DATA3

xxxxxxxx

10xxxxxx

xxxxxx11

Digital Outputs

The nine digital outputs, DOUT8 to DOUT0, are used to

control the status or function of radio subsections external to

the ACE9030 and are controlled by a Normal type command

with a logic “1” setting the output to HIGH or ON and a logic “0”

giving LOW or OFF.

Outputs DOUT0 and DOUT1 are power switches from

DDX to supply Front-End circuits. Both are forced to OFF in

Sleep mode.

Fig. 12 Lock Detect Block Diagram

Lock Detect Filter

The Lock Detect Filter processes the phase errors in both

synthesisers to give a clean signal to put onto the bus as a

single bit added to the ADC read response.

In the synthesiser section of the ACE9030 the time

differences between the active edges of the outputs of the

programmable dividers and of the reference divider are com-

pared with a window of two cycles of the reference clock, XO,

from the crystal oscillator. If a loop has a time difference, or

phase error, larger than this window then that loop is deemed

unlocked and its lock signal is held low for a whole comparison

period, giving a Main Lock and an Auxiliary Lock signal. When

both synthesisers are active the error signals are combined by

an AND function to give the internal signal LOCK. If either

synthesiser is powered down its lock is disregarded and if both

are powered down the ACE9030 will always give LOCK at

LOW, the unlocked state, to be output on the bus. This final

signal LOCK is normally HIGH to indicate locked loops but will

pulse low for one or more comparison periods when an active

synthesiser is unlocked.

Outputs DOUT2 to DOUT4 are logic level outputs to

control various functions in the cellphone. DOUT2 and

DOUT3 are forced to HIGH and DOUT4 is forced to high

impedance in Sleep mode.

Outputs DOUT5 to DOUT7 are low current outputs with

reduced voltage swing to control power down in the ACE9010

and ACE9020. All three are forced to LOW in Sleep mode.

Output DOUT8 can be driven by the buffered Band-gap

based ADC reference voltage and is included for test and

setting-up purposes, as well as for driving a temperature

sensing thermistor read through one of the ADC channels.

DOUT8 is forced to high impedance in Sleep mode.

The control formats are Normal commands:

DATA1

DATA2

DATA3

7 D6 D5 D4 D3 D2 D1 D0

01xxx1xx

xxxxxxxx

where DATA1 bits 7 to 0 control DOUT7 to DOUT0 respec-

tively when enabled by DATA2 bit 2, and:

DATA1

DATA2

DATA3

xxxxxxxx

01xxxxxx

xx D

5 xxxxx

where DATA3 bit 5 controls DOUT8 directly.

MAIN COMP.

FREQUENCY

MAIN PROG.

DIVIDER

AUX. PROG.

DIVIDER

AUX. COMP.

FREQUENCY

COMPARE

TIMING

COMPARE

TIMING

ADD +2X0

WINDOW

ADD +2X0

WINDOW

(1.008 MHz)

504 kHz

LOCK

LEVEL SET

FROM BUS

TO BUS

THRESHOLD

COMPARATOR

7 BIT

COUNTER

WINDOW

COUNT: 80/84

: 2

WINDOW SET FROM BUS

START/STOP

ACE9030M/IW/FP2Q Fiches technique(PDF) 15 Page - Mitel Networks Corporation

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