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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AX2000 Fiches technique(PDF) 107 Page - Microsemi Corporation |
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AX2000 Fiches technique(HTML) 107 Page - Microsemi Corporation |
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107 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 93 Table 2-92 • Eight RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Write Mode tWDASU Write Data Setup vs. WCLK 5.78 6.58 7.74 ns tWDAHD Write Data Hold vs. WCLK 0.00 0.00 0.00 ns tWADSU Write Address Setup vs. WCLK 5.78 6.58 7.74 ns tWADHD Write Address Hold vs. WCLK 0.00 0.00 0.00 ns tWENSU Write Enable Setup vs. WCLK 5.78 6.58 7.74 ns tWENHD Write Enable Hold vs. WCLK 0.00 0.00 0.00 ns tWCKH WCLK Minimum High Pulse Width 0.75 0.75 0.75 ns tWCLK WCLK Minimum Low Pulse Width 5.13 5.13 5.13 ns tWCKP WCLK Minimum Period 5.88 5.88 5.88 ns Read Mode tRADSU Read Address Setup vs. RCLK 6.75 7.69 9.04 ns tRADHD Read Address Hold vs. RCLK 0.00 0.00 0.00 ns tRENSU Read Enable Setup vs. RCLK 6.75 7.69 9.04 ns tRENHD Read Enable Hold vs. RCLK 0.00 0.00 0.00 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 3.39 3.86 4.54 ns tRCK2RD2 RCLK-To-OUT (Non-Pipelined) 4.93 5.62 6.61 ns tRCLKH RCLK Minimum High Pulse Width 0.73 0.73 0.73 ns tRCLKL RCLK Minimum Low Pulse Width 5.77 5.77 5.77 ns tRCKP RCLK Minimum Period 6.50 6.50 6.50 ns Note: Timing data for these eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use Microsemi’s timing software. |
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