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AX2000 Fiches technique(PDF) 40 Page - Microsemi Corporation

No de pièce AX2000
Description  Axcelerator Family FPGAs
PDF  262 Pages
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Fabricant  MICROSEMI [Microsemi Corporation]
Site Internet  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

AX2000 Fiches technique(HTML) 40 Page - Microsemi Corporation

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Detailed Specifications
2- 26
R e v i sio n 1 8
Timing Characteristics
Table 2-22 • 3.3 V LVTTL I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Units
LVTTL Output Drive Strength = 1 (8 mA) / Low Slew Rate
tDP
Input Buffer
1.68
1.92
2.26
ns
tPY
Output Buffer
14.28
16.27
19.13
ns
tENZL
Enable to Pad Delay through the Output Buffer—Z to
Low
15.25
17.37
20.42
ns
tENZH
Enable to Pad Delay through the Output Buffer—Z to
High
14.26
16.24
19.09
ns
tENLZ
Enable to Pad Delay through the Output Buffer—Low
to Z
1.56
1.57
1.58
ns
tENHZ
Enable to Pad Delay through the Output Buffer—High
to Z
1.95
1.96
1.97
ns
tIOCLKQ
Sequential Clock-to-Q for the I/O Input Register
0.67
0.77
0.90
ns
tIOCLKY
Clock-to-output Y for the I/O Output Register and the
I/O Enable Register
0.67
0.77
0.90
ns
tSUD
Data Input Set-Up
0.23
0.27
0.31
ns
tSUE
Enable Input Set-Up
0.26
0.30
0.35
ns
tHD
Data Input Hold
0.00
0.00
0.00
ns
tHE
Enable Input Hold
0.00
0.00
0.00
ns
tCPWHL
Clock Pulse Width High to Low
0.39
0.39
0.39
ns
tCPWLH
Clock Pulse Width Low to High
0.39
0.39
039
ns
tWASYN
Asynchronous Pulse Width
0.37
0.37
0.37
ns
tREASYN
Asynchronous Recovery Time
0.13
0.15
0.17
ns
tHASYN
Asynchronous Removal Time
0.00
0.00
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.23
0.27
0.31
ns
tPRESET
Asynchronous Preset-to-Q
0.23
0.27
0.31
ns



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