AX2000 datasheet(14/262 Pages) MICROSEMI

14 / 262 page

General Description

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Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The

probe circuitry is accessed and controlled via Silicon Explorer II, Microsemi's integrated verification and

logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG

port (See "Silicon Explorer II Probe Interface" on page 2-109).

Summary

Microsemi’s Axcelerator family of FPGAs extends the successful SX-A architecture, adding embedded

RAM/FIFOs, PLLs, and high-speed I/Os. With the support of a suite of robust software tools, design

engineers can incorporate high gate counts and fixed pins into an Axcelerator design yet still achieve

high performance and efficient device utilization.

Related Documents

Application Notes

Simultaneous Switching Noise and Signal Integrity

http://www.microsemi.com/soc/documents/SSN_AN.pdf

Axcelerator Family PLL and Clock Management

http://www.microsemi.com/soc/documents/AX_PLL_AN.pdf

Implementation of Security in Actel Antifuse FPGAs

http://www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

http://www.microsemi.com/soc/documents/libguide_UG.pdf

SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder

http://www.microsemi.com/soc/documents/genguide_ug.pdf

Silicon Sculptor II User’s Guide

http://www.microsemi.com/soc/documents/silisculptII_sculpt3_ug.pdf

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf

Understanding Actel Antifuse Device Security

http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf

Miscellaneous

Libero IDE flow diagram

http://www.microsemi.com/soc/products/tools/libero/flow.html

AX2000 Fiches technique(PDF) 14 Page - Microsemi Corporation