CHR71000 datasheet(28/54 Pages) AMSOSRAM

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CHR71000

Functional description

Datasheet • PUBLIC • Document Feedback

DS000427 • v2-01 • 2026-Mar-18

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Figure 16: Timing with external signals

The exact timing of these three signals and their relation to the timing of the other digital inputs

is specified in more detail in section 7.3.2.2.

Because of the 4T shared pixel architecture, a number of extra rules apply to the timing of

CLK_Y, SYNC_Y_READ and SYNC_Y_INTE:

•

The integration on a line can only start 2 line times after that line has been read out. This

means that if the address settings are unchanged between two frames, there must be two

line times with function “Reset” after the line “First line” before a line with function

“Integration” can start.

•

The y-start address can only change to a new value 2 line times after the line addressed

by that new value has been read out.

INTE 1

INTE 2

ROT 1

ROT 2

ROT 3

ROT 4

Frame 1 Integration

Frame 1 Readout

ROT 1

ROT 2

ROT 3

ROT 4

Frame 2 Readout

Frame 2 Integration

IMC_CLK_Y

IMC_SYNC_Y_READ

IMC_SYNC_Y_INTE

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