VS1103B datasheet(55/61 Pages) ETC2

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VLSI

Solution

VS1103b

VS1103B

8. VS1103B REGISTERS

8.12.3 Conﬁguration TIMER ENABLE

TIMER ENABLE Bits

Name

Bits

Description

TIMER EN T1

Enable timer 1

TIMER EN T0

Enable timer 0

8.12.4 Timer X Startvalue TIMER Tx[L/H]

The 32-bit start value TIMER Tx[L/H] sets the initial counter value when the timer is reset. The timer

interrupt frequency ft =

c+1 where fi is the master clock obtained with the clock divider (see Chap-

ter 8.12.2 and c is TIMER Tx[L/H].

Example: With a 12 MHz master clock and with TIMER CF CLKDIV=3, the master clock fi = 3MHz.

If TIMER TH=0, TIMER TL=99, then the timer interrupt frequency ft = 3MHz

99+1 = 30kH z.

8.12.5 Timer X Counter TIMER TxCNT[L/H]

TIMER TxCNT[L/H] contains the current counter values. By reading this register pair, the user may get

knowledge of how long it will take before the next timer interrupt. Also, by writing to this register, a

one-shot different length timer interrupt delay may be realized.

8.12.6 Interrupts

Each timer has its own interrupt, which is asserted when the timer counter underﬂows.

Version 1.01, 2007-09-03

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