VLSI
Solution
y
VS1103b
VS1103B
6. FUNCTIONAL DESCRIPTION
When SM DIFF is set, the player inverts the left channel output. For a stereo input this creates virtual
surround, and for a mono input this creates a differential left/right signal.
If SM RECORD PATH is set, ADPCM recording is performed from the A/D stream at 8 kHz, otherwise
the Mixer output is recorded at 44.1 kHz. This bit is only valid if SM ADPCM is set.
Software reset is initiated by setting SM RESET to 1. This bit is cleared automatically.
To stop decoding a MIDI file set SM OUTOFMIDI, and send data until SM OUTOFMIDI has cleared. If
SM OUTOFMIDI is set while MIDI decoding has not been going on, the register bit will not be cleared
before the few first words of the next MIDI file (or zeros) have been sent to the decoder.
Bit SM PDOWN sets VS1103b into software powerdown mode where the only operational software
part is the control bus handler. Note: software powerdown is not nearly as power efficient as hardware
powerdown activated with the XRESET pin.
If SM TESTS is set, SDI tests are allowed. For more details on SDI tests, look at Chapter 7.8.
SM ICONF specifies the configuration of the data input streams. The following table shows its bits.
SM ICONF
S1 Port
Stream1
S2 Port
Stream2
0
SDI
MIDI
SCI
ADPCM
1
SCI
MIDI
SDI
ADPCM
2
UART/SDI
RT-MIDI/RT-SDI
SCI
ADPCM
3
UART
RT-MIDI
SDI
ADPCM
When SM ICONF is set to 2, Real Time MIDI messages can be sent either through the UART or SDI.
If sent through UART, the standard MIDI protocol and date speed (31250 bit/s) is used. If send through
SDI, the protocol is otherwise the same, but every byte must either be preceded or followed by a zero
byte (but only one of these two alternative zero byte orders may be used at a time). So, a message that
would be sent as 0x92 0x37 0x73 through normal MIDI, would become 0x92 0x00 0x37 0x00 0x73 0x00
if sent through SDI.
NOTE! If you change SM ICONF, a software reset is performed as if you had also set SM RESET!
SM DACT defines the active edge of data clock for SDI. When ’0’, data is read at the rising edge, when
’1’, data is read at the falling edge.
When SM SDIORD is clear, bytes on SDI are sent as a default MSb first. By setting SM SDIORD, the
user may reverse the bit order for SDI, i.e. bit 0 is received first and bit 7 last. Bytes are, however, still
sent in the default order. This register bit has no effect on the SCI bus.
Setting SM SDISHARE makes SCI and SDI share the same chip select, as explained in Chapter 5.2, if
also SM SDINEW is set.
Setting SM SDINEW will activate VS1002 native serial modes as described in Chapters 5.2.1 and 5.4.2.
Note, that this bit is set as a default when VS1103b is started up.
Version 1.01, 2007-09-03
30
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