IMX8MPCEC datasheet(2/111 Pages) NXP

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i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

i.MX 8M Plus introduction

The i.MX 8M Plus is very versatile presenting multiple displays and high-speed interfaces as well as mul-

tiple memory interfaces.

It is built to meet the needs for Smart Home, Building, City and Industry 4.0 applications.

Table 1. Features (Sheet 1 of 4)

Subsystem

Features

Cortex®-A53 MPCore platform

Quad Cortex®-A53 processors operation up to 1.8 GHz

• 32 KB L1 Instruction Cache

• 32 KB L1 Data Cache

• Media Processing Engine (MPE) with Arm® NEONTM technology supporting the

Advanced Single Instruction Multiple Data architecture

• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture

Support of 64-bit Arm® v8-A architecture

512 KB unified L2 cache

Cortex®-M7 core platform

• Microcontroller available for customer application

• Real-time processing

•Cortex®-A53 complex off loading

• Low power operation

Cortex®-M7 CPU operating up to 800 MHz

• 32 KB L1 Instruction Cache

• 32 KB L1 Data Cache

• 256 KB tightly coupled memory (TCM)

Image Sensor Processor (ISP)

375 Mpixel/s HDR ISP supporting configurations, such as 12MP@30fps, 4kp45, or

2x 1080p80

External memory interface

32-bit DRAM interfaces:

• LPDDR4-4000

• DDR4-3200

• Inline ECC on the DDR bus

8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to

62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200

MB/sec)

eMMC 5.1 Flash (2 interfaces: uSDHC1 and uSDHC3)

SPI NOR Flash (3 interfaces)

FlexSPI Flash with support for XIP (for Cortex®-M7 in low-power mode) and support

for either one Octal SPI, or parallel read mode of two identical Quad SPI FLASH

devices. It also supports both Serial NOR and Serial NAND flash using the FlexSPI.

On-chip memory

Boot ROM (256 KB)

On-chip RAM (868 KB):

• OCRAM_A: 256 KB inside AUDIOMIX

• OCRAM: 576 KB inside SUPERMIX

• OCRAM_S: 36 KB inside SUPERMIX

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