DP83821 datasheet(12/86 Pages) NSC

12 / 86 page

3.0 Functional Description (Continued)

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Figure 3-4 Target Read Operation

3.3.2 Target Write

A Target Write operation starts with the system generating

FRAMEN, Address, and Command (0011b or 0111b). See

Figure 3-5. If the upper 24 bits on the address bus match

CFGIOA:IOBASE (for I/O reads) or CFGMA:MEMBASE

(for memory reads), the DP83821 will generate DEVSELN

2 clock cycles later.

On the 2nd cycle after the assertion of DEVSELN, the

device will monitor the IRDYN signal. If IRDYN is asserted

at that time, the DP83821 will assert TRDYN. On the next

clock the 32-bit double word will be latched in, and TRDYN

will be forced HIGH for 1 cycle and then tri-stated.

Note: Target write operations must be 32-bits wide.

If FRAMEN is asserted beyond the assertion of IRDYN, the

DP83821 will still latch the first double word as described

above, but will also issue a Disconnect. That is, it will

assert the STOPN signal with TRDYN. STOPN will remain

asserted until FRAMEN is detected as deasserted.

Figure 3-5 Target Write Operation

Addr

Data

CLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

Addr

Data

CLK

FRAMEN

AD[31:0]

C/BEN[3:0]

IRDYN

TRDYN

DEVSELN

PAR

PERRN

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