DP83821 datasheet(28/86 Pages) NSC

28 / 86 page

3.0 Functional Description (Continued)

www.national.com

was used to describe the packet, then completion

status is updated only in the last descriptor.

Intermediate descriptors only have the OWN bits

modified.

9. If the link field of the descriptor is non-zero, the state

machine advances to the next descriptor and

continues. When reading the next descriptor, if the

OWN bit is not set, the state machine will halt and

wait for TXEN to be set again.

10. If the link field is NULL, the transmit state machine

suspends, waiting for the TXEN bit in the CR register

to be set. If the TXDP register is written to, the CTDD

flag will be cleared. When the TXEN bit is set, the

state machine will examine CTDD. If CTDD is set,

the state machine will "refresh" the link field of the

current descriptor. It will then follow the link field to

any new descriptors that have been added to the end

of the list. If CTDD is clear (implying that TXDP has

been written to), the state machine will start by

reading in the descriptor pointed to by TXDP.

3.13.3.3 Transmit Data Flow with Priority Queueing

The transmit architecture with Priority Queueing is the

same with a few minor differences:

— Driver keeps a separate list for each descriptor queue.

— When setting the TXEN bit, the driver must also set the

appropriate TXPRI bit for the priority queue or queues to

which descriptors are being appended.

— Upon completion of a packet, the transmit state machine

first determines what the highest priority descriptor is

available based on non-zero link fields and TXEN bits. It

then follows the appropriate link or reads a new

descriptor for the next packet to be transmitted.

3.13.4 Receive Architecture

The receive architecture is as "symmetrical" to the transmit

architecture as possible. As is done in the transmitter, the

receive architecture can support a single descriptor queue

or multiple descriptor queues for handling priority traffic.

When the amount of receive data in the RxDataFIFO is

more than the RxDrainThreshold, or the RxDataFIFO

contains a complete packet, then the state machine begins

filling received buffers in host memory.

Figure 3-17 Receive Architecture without Priority Queueing

Without Priority Queueing, the device will transfer packets

to a single Descriptor list. Only one descriptor pointer is

required. The receive buffer manager prefetches receive

descriptors to prepare for incoming packets. When the

RXEN bit is set to 1 in the CR register (regardless of the

current state), and the DP83821 receive state machine is

idle, then DP83821 will read the contents of the descriptor

referenced by RXDP into the Rx Descriptor Cache. The Rx

Descriptor Cache allows the DP83821 to read an entire

descriptor in a single burst, and reduces the number of bus

accesses required for fragment information to 1. The

DP83821 Rx Descriptor Cache holds a single buffer

pointer/count combination.

Receive Descriptor List

Current Rx Desc Ptr

Software/Memory

Hardware

Rx Data FIFO

link

bufptr

cmdsts

Rx DMA

bufptr

Packet

RxHead

link

Rx Desc Cache

link

bufptr

cmdsts

Packet

link

bufptr

cmdsts

Packet

DP83821 Fiches technique(PDF) 28 Page - National Semiconductor (TI)

DP83821 Fiches technique(HTML) 28 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Fiches technique Télécharger

Lien URL