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DP83821 Fiches technique(PDF) 76 Page - National Semiconductor (TI) |
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DP83821 Fiches technique(HTML) 76 Page - National Semiconductor (TI) |
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76 / 86 page ![]() 5.0 DC and AC Specifications (Continued) 76 www.national.com 5.2.5 POR PCI Inactive 5.2.6 PCI Bus Cycles The following table parameters apply to ALL the PCI Bus Cycle Timing Diagrams contained in this section. Number Parameter Min Typ Units 5.2.5.1 VDD stable to EE access VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. 60 us Number Parameter Min Typ Units 5.2.6.1 Input Setup Time 7 ns 5.2.6.2 Input Hold Time 0 ns 5.2.6.3 Output Valid Delay 2 11 ns 5.2.6.4 Output Float Delay (toff time) 28 ns 5.2.6.5 Input Setup Time for GNTN - point to point 10 ns EESEL VDD T1 |
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