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DP83821 Fiches technique(PDF) 7 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce DP83821
Description  10/100/1000 Mb/s PCI Ethernet Network Interface Controller
PDF  86 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83821 Fiches technique(HTML) 7 Page - National Semiconductor (TI)

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2.0 Pin Descriptions (Continued)
Clock Interface
Symbol
Pin No(s)
Direction
Description
X1
122
I
Crystal/Oscillator Input: This pin is the primary clock reference input for the
DP83821 IC and must be connected to a 25MHz 0.005% (50ppm) clock source.
The DP83821 device supports either an external crystal resonator connected
across pins X1 and X2, or an external CMOS-level oscillator source connected
to pin X1 only.
X2
121
O
Crystal Output: This pin is used in conjunction with the X1 pin to connect to an
external 25MHz crystal resonator device. This pin must be left unconnected if
an external CMOS oscillator clock source is utilized. For more information see
the definition for pin X1.
Phy And General Purpose Interface
Symbol
Pin No(s)
Direction
Description
GP1DUP
131
I/O
General Purpose Pin 1 or Duplex Status: By default, this pin can be used to
input the Full Duplex status from an external Phy. The pin can also be
programmed as a general purpose I/O. This pin pad has an internal weak pull
up.
GP2
127
I/O
General Purpose Pin 2: This pin is a general purpose I/O pin that can be
programmed as an input or output. This pin has an internal weak pull up.
GP3
128
I/O
General Purpose Pin 3: This pin is a general purpose I/O pin that can be
programmed as an input or output. This pin has an internal weak pull up.
GP4
129
I/O
General Purpose Pin 4: This pin is a general purpose I/O pin that can be
programmed as an input or output. This pin has an internal weak pull up.
GP5
130
I/O
General Purpose Pin 5: This pin is a general purpose I/O pin that can be
programmed as an input or output. This pin has an internal weak pull up.
PHYLNK
132
I
Phy Link Status: This can be used to input the Phy Link Status. This allows the
value to be read back from the MAC register space.
SPD100
133
I
100 Mb/s Speed Status: This can be used to input the 100 Mb/s Speed Status
from an external phy. This is used along with the SPD1000 bit to determine
current speed status of the Phy.
SPD1000
134
I
1000 Mb/s Speed Status: This can be used to input the 1000 Mb/s Speed
Status from an external phy. This is used along with the SPD100 bit to
determine current speed status of the Phy.
PHYRSTN
172
O
Phy Reset: This pin can be used to reset an External Phy.
Serial EEPROM Interface
Symbol
Pin No(s)
Direction
Description
EESEL
91
O
EEPROM Chip Select: This signal is used to enable the external EEPROM
device.
MA4/EECLK
109
O
EEPROM Clock: During an EEPROM access (EESEL asserted), this pin is an
output used to drive the serial clock to an external EEPROM device.



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