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DP83821 Fiches technique(PDF) 35 Page - National Semiconductor (TI) |
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DP83821 Fiches technique(HTML) 35 Page - National Semiconductor (TI) |
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35 / 86 page ![]() 35 www.national.com 4.0 Register Set (Continued) 4.1.3 Configuration Revision ID Register This register stores the silicon revision number, revision number of software interface specification and lets the configuration software know that it is an Ethernet controller in the class of network controllers. 4.1.4 Configuration Latency Timer Register This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size. DP83821 Bus Master Operations: Based on cache line size, the DP83821 will use the following PCI commands for bus mastered transfers: 0110 - Mem Read Single dword read transfers 1110 - Mem Read Line Read More than 1 dword but not across a cacheline boundary 1100 - Mem Read Multiple Read transfers that cross a cacheline boundary 0111 - Mem Write Writes that do not exactly overwrite 1 or more cachelines 1111 - Mem Write Invalidate Writes that exactly overwrite 1 or more cachelines Tag: CFGRID Size: 32 bits Hard Reset: 02000000h Offset: 08h Access: Read Only Soft Reset: Unchanged bit tag description usage 31-24 BASECL Base Class Returns 02h which specifies a network controller. 23-16 SUBCL Sub Class Returns 00h which specifies an Ethernet controller. 15-8 PROGIF Programming IF Returns 00h which specifies the first release of the DP83821. 7-0 REVID Silicon Revision Returns 00h which specifies the silicon revision. Tag: CFGLAT Size: 32 bits Hard Reset: 00000000h Offset: 0Ch Access: Read Write Soft Reset: Unchanged bit tag description usage 31 BISTCAP BIST Capable Reads will always return 0. 30 BISTEN BIST Enable Reads will return a 0, writes are ignored. 29-16 Reserved Reads will return a 0, writes are ignored. 15-8 LAT Latency Timer Set by software to the number of PCI clocks that DP83821 may hold the PCI bus. 7-0 CLS Cache Line Size Set to the value of the system cache line size in dwords. Acceptable values are powers of 2 less than or equal to 128. All other values will be recognized as 0. |
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