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DP83821 Fiches technique(PDF) 33 Page - National Semiconductor (TI) |
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DP83821 Fiches technique(HTML) 33 Page - National Semiconductor (TI) |
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33 / 86 page ![]() 33 www.national.com 4.0 Register Set 4.1 Configuration Registers The DP83821 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the DP83821. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to their hardware reset state. For all unused registers, writes are ignored, and reads return 0. Table 4-1 Configuration Register Map 4.1.1 Configuration Identification Register This register identifies the DP83821 Controller to PCI system software. offset tag description access 00h CFGID Configuration Identification Register RO 04h CFGCS Configuration Command and Status Register R/W 08h CFGRID Configuration Revision ID Register RO 0Ch CFGLAT Configuration Latency Timer Register RO 10h CFGIOA Configuration IO Base Address Register R/W 14h CFGMA Configuration Memory Address Register R/W 18 CFGMA1 Configuration Memory Address High Dword Register R/W 1Ch-28h Reserved (reads return zero) 2Ch CFGSID Configuration Subsystem Identification Register RO 30h CFGROM Boot ROM configuration register R/W 34h CAPPTR Capabilities Pointer Register RO 38h Reserved (reads return zero) 3Ch CFGINT Configuration Interrupt Select Register R/W 40h PMCAP Power Management Capabilities Register RO 44h PMCS Power Management Control and Status Register R/W 48-FFh Reserved (reads return zero) Tag: CFGID Size: 32 bits Hard Reset: 0022100B Offset: 00h Access: Read Only Soft Reset: Unchanged bit tag description usage 31-16 DEVID Device ID This field is read-only and is set to the device ID assigned by NSC to the DP83821, which is 0022h. 15-0 VENID Vendor ID This field is read-only and is set to a value of 100Bh which is National Semiconductor's PCI Vendor ID. |
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