IMX7SCEC datasheet(75/152 Pages) NXP

75 / 152 page

Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

For DDR Toggle mode, Figure 41 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will

sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which is

provided by an internal DPLL. The delay value of this register can be controlled by GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 7Dual

Application Processor Reference Manual [IMX7DRM]). Generally, the typical delay value is equal to 0x7

which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored,

the delay value should be made larger to compensate the board delay.

4.10

External peripheral interface parameters

The following subsections provide information on external peripheral interfaces.

4.10.1

ECSPI timing parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing

parameters for master and slave modes.

NF28

Data write setup

tDS6

0.25

× tCK - 0.32

—

NF29

Data write hold

tDH6

0.25

× tCK - 0.79

—

NF30

NAND_DQS/NAND_DQ read setup skew

tDQSQ7

—3.18

NF31

NAND_DQS/NAND_DQ read hold skew

tQHS7

—3.27

1 The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

AS minimum value can be 0, while DS/DH minimum value is 1.

3 T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).

4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

5 PRE_DELAY+1)

≥ (AS+DS)

6 Shown in Figure 42.

7 Shown in Figure 43.

Table 51. Toggle mode timing parameters1(continued)

Parameter

Symbol

Timing

T = GPMI Clock Cycle

Unit

Min.

Max.

IMX7SCEC Fiches technique(PDF) 75 Page - NXP Semiconductors

IMX7SCEC Fiches technique(HTML) 75 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL