IMX7SCEC datasheet(61/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

1 All measurements are in reference to Vref level.

2 Measurements were done using balanced load and 25 Ω resistor from outputs to VDD_REF.

Figure 25 shows the DDR3 write timing diagram. The timing parameters for this diagram appear in

Table 41.

Figure 25. DDR3 write cycle

1 To receive the reported setup and hold values, write calibration should be performed in order to locate the DRAM_SDQSx_P in

the middle of DRAM_DATAxx window.

2 All measurements are in reference to Vref level.

3 Measurements were taken using balanced load and 25 Ω resistor from outputs to DDR_VREF.

Table 41. DDR3 write cycle

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

DDR17

DRAM_DATAxx and DRAM_DQMx setup time to DRAM_SDQSx_P

(differential strobe)

tDS

225

—

DDR18

DRAM_DATAxx and DRAM_DQMx hold time to DRAM_SDQSx_P

(differential strobe)

tDH

250

—

DDR21

DRAM_SDQSx_P latching rising transitions to associated clock edges

tDQSS

-0.25

+0.25

tCK

DDR22

DRAM_SDQSx_P high level width

tDQSH

0.45

0.55

tCK

DDR23

DRAM_SDQSx_P low level width

tDQSL

0.45

0.55

tCK

DRAM_SDCLKx_P

DRAM_SDCLKx_N

DRAM_SDQSx_P

DRAM_DATAxx

DRAM_DQMx

Data

DDR17

DDR18

DDR21

DDR23

DDR22

(output)

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