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IMX7SCEC Fiches technique(PDF) 59 Page - NXP Semiconductors

No de pièce IMX7SCEC
Description  i.MX 7Solo Family
PDF  152 Pages
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7SCEC Fiches technique(HTML) 59 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
59
MAXDTI
MAXIMUM delay from
EIM_DTACK_B to its internal
FF + 2 cycles for
synchronization
10
—
—
ns
WE47
EIM_DTACK_B Active to
EIM_CSx_B Invalid
MAXCO – MAXCSO +
MAXDTI
MAXCO –
MAXCSO +
MAXDTI
—ns
WE48
EIM_CSx_B Invalid to
EIM_DTACK_B Invalid
00
—
ns
1 For more information on configuration parameters mentioned in this table, see the i.MX 7Solo Application Processor Reference
Manual (IMX7SRM).
2 In this table, CSA means WCSA when write operation or RCSA when read operation.
3 In this table, CSN means WCSN when write operation or RCSN when read operation.
4 t is axi_clk cycle time.
5 In this table, ADVN means WADVN when write operation or RADVN when read operation.
6In this table, ADVA means WADVA when write operation or RADVA when read operation.
Table 39. EIM asynchronous timing parameters table relative chip to select(continued)
Ref No.
Parameter
Determination by
Synchronous measured
parameters1
Min
Max
Unit



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