RM0319 datasheet(101/368 Pages) STMICROELECTRONICS

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RM0319

Parallel NAND Flash controller (FSMC)

Doc ID 022640 Rev 3

101/368

Parallel NAND Flash controller (FSMC)

This chapter focuses on FSMC functionality and operation.

For technical details about the programmable registers related to the FSMC, refer to the

FSMC registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

8.1

Overview

SPEAr320S provides a Flexible Static Memory Controller (FSMC) which is intended to

interface an AHB bus to external parallel NAND Flash memories (8/16 bit).

Note:

The 16-bit NAND interface is available when the in SPEAr320S is configured in automation

expansion mode (see Section 32: Reconfigurable array subsystem (RASCFG) and the pin

description section of the SPEAr320S datasheet).

The controller translates the AHB protocol into external parallel NAND Flash protocol. It

meets the timings of the external devices, slowing down and counting an appropriate

number of HCLK (AHB clock) cycles to complete the transaction to the external device.

Note:

The external storage device cannot be faster than one AHB cycle.

8.2

Main features

●

AHB slave interface

●

Interfaces AHB with parallel NAND Flash devices

●

Performs only one access at a time;

●

Provides programmable timings to support a wide range of devices:

–

programmable wait states (up to 31),

–

programmable bus turn around cycles (up to 15),

–

programmable output enable and write enable delays (up to 15).

●

Can be interfaced with four external devices (four chip select pins available);

●

Offers an external asynchronous wait control;

●

Offers configurable size at reset for boot memory bank using SPEAr320S configuration

registers

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