OR3LP26B datasheet(13/184 Pages) AGERE

13 / 184 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

OR3LP26B Overview (continued)

Independent data paths exist for the Master and Target controllers. This allows for separate operation of Master

and Target functions, and the capability for a Master to talk to a Target on the same device.

In dual-port mode, the Master and Target controllers share two 64-bit data paths, one in each direction, between

the FIFOs and the FPGA logic. This provides for full-rate transfers in both 32- and 64-bit PCI bus operation.

Quad-port mode provides two 32-bit data paths for each controller: one in each direction. This mode allows for

simultaneous reads and writes on either the Master or Target controller.

Diagrams for dual-port and quad-port operation are shown in Figure 1.

5-6368(F).e

Note: User I/O pin count includes three ExpressCLK pins.

Figure 1.

ORCA OR3LP26B PCI FPSC Block Diagram

Embedded Core Options/FPGA Configuration

In addition to the Series 3 FPGA configuration modes (less Master parallel), the OR3LP26B can also be configured

via the PCI bus. Configuration as discussed here has two meanings. There is configuration of the FPGA logic, and

there is configuration of the options available in the embedded core. Both are accomplished through the FPGA

configuration process (some PCI configuration options may also be set via registers within the PCI bus core).

Readback of FPGA and PCI core options is also possible using the PCI bus or Series 3 FPGA readback modes.

The PCI bus core will be functional in the default PCI bus configuration space, as defined in the PCI bus 2.2 speci-

fication, prior to an initial configuration of the FPGA logic or the embedded core options.

113 USER I/O PADS

OR3T SERIES FPGA

18 ROWS x 28 COLUMNS

USER

I/O PADS

USER

I/O PADS

PCI

MASTER/TARGET

INTERFACE

PCI

BUS

DATA CONTROL

AND

MULTIPLEXING

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

32 DEEP

FIFO

MASTER

113 USER I/O PADS

OR3T SERIES FPGA

18 ROWS x 28 COLUMNS

USER

I/O PADS

USER

I/O PADS

64-bit x

32 DEEP

FIFO

PCI

MASTER/TARGET

INTERFACE

PCI

BUS

DATA CONTROL

AND

MULTIPLEXING

MASTER

64-bit x

32 DEEP

FIFO

MASTER

64-bit x

16 DEEP

FIFO

TARGET

64-bit x

16 DEEP

FIFO

TARGET

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