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OR3LP26B Fiches technique(PDF) 82 Page - Agere Systems

No de pièce OR3LP26B
Description  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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OR3LP26B Fiches technique(HTML) 82 Page - Agere Systems

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ORCA OR3LP26B FPSC
Data Sheet
Embedded Master/Target PCI Interface
March 2000
82
Lucent Technologies Inc.
Lucent Technologies Inc.
PCI Bus Core Detailed Description Quad Port (continued)
Table 26. Address Cycle Sequences for Various Operations
Operation
Address
Mode
Supplied
Address
New Burst
Length
Address Cycle
Sequence
(Once Only)
Data Cycle
Sequence
(Repeats)
Master Write
SA/DA
31:0
NA
A
CD
DA
63:0
NA
A, B
CD
Master Read
SA/DA
15:0
No
E
I, J
SA/DA
(none)
Yes
F
I, J
SA/DA
31:0
Yes
F, G
I, J
DA
63:0
Yes
F, G, H
I, J
Target Write
SA/DA
31:0
NA
K
M, N
DA
63:0
NA
K, L
M, N
Target Read
SA/DA
31:0
NA
K
O, P
DA
63:0
NA
K, L
O, P



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