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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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SPEAR1340 Fiches technique(PDF) 6 Page - STMicroelectronics |
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SPEAR1340 Fiches technique(HTML) 6 Page - STMicroelectronics |
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6 / 200 page  Description SPEAr1340 6/200 Doc ID 023063 Rev 4 1 Description The SPEAr1340 device is a system-on-chip belonging to the SPEAr® (Structured Processor Enhanced Architecture) family of embedded microprocessors. The product is suitable for consumer and professional applications where an advanced human machine interface (HMI) combined with high performance are required, such as low-cost tablets, thin clients, media phones and industrial/printer smart panels. The device is hardware-compliant to the support of both real-time (RTOS) and high-level (HLOS) operating systems, such as Android, Linux and Windows Embedded Compact 7. The architecture of SPEAr1340 is based on several internal components, communicating through a multilayer interconnection matrix (BUSMATRIX). This switching structure enables different data flows to be carried out concurrently, improving the overall platform efficiency. In particular, high-performance master agents are directly interconnected with the DDR memory controller in order to reduce access latency. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal weighted round-robin (WRR) arbitration scheme. Figure 1. SPEAr1340 architectural block diagram FPU PTM Cortex A9 CPU 32 KB ICache 32 KB DCache Interrupt Controller 512 KBL2 Cache ACP Cache Transfers Snoop Filtering Timer & Watchdog CPU 0 AXI Bus Master 0 AXI Bus Master 1 Coresight Global Timer Timer & Watchdog CPU 1 SCU MPCore CPU 0 DisplayCtrl 2D/3D GPU Video Decoder Video Encoder CameraI/F (4x) Video Input I2S Audio I/F (8 in, 8 out) S/PDIF Audio I/F USB 2.0 Host Ctrl USB 2.0 OTG Ctrl USB PHYs Giga/Fast Ethernet Ctrl PCIe Ctrl SATA Ctrl PHY Graphics, video, audio Highspeed connectivity USB 2.0 Host Ctrl BUSMATRIXInterconnect GPIO XGPIO I2C (2x) SSP UART (2x) KBD CEC (2x) ADC PWM (4x) RTC Lowspeed connectivity DDR2/3 Ctrl Static Memory Ctrl Serial Memory I/F Memory cardI/F Memory FPU PTM Cortex A9 CPU 32 KB ICache 32 KB DCache CPU 1 BootROM SRAMs DMA Ctrl (2x) Security Coprocessor Reset & clock Generator PowerControl Configuration registers Timers JTAG Trace THSENS OTP Opt. Battery |
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