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STA382BW Fiches technique(PDF) 152 Page - STMicroelectronics

No de pièce STA382BW
Description  Sound Terminal® 2.1-channel high-efficiency digital audio system
PDF  172 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA382BW Fiches technique(HTML) 152 Page - STMicroelectronics

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Register description: Sound Terminal compatibility
STA382BW
152/172
Doc ID 022783 Rev 1
7.21
Extended coefficient range up to -4...4 (address 0x49, 0x4A)
Biquads from 1 to 7 have in the STA382BW the possibility to extend the coefficient range
from [-1,1) to [-4..4) which allows the implementation of high-shelf filters that may require a
coefficient dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated
Each biquad has its independent setting according to the following table.
Table 171.
Coefficients extended range configuration
In this case the user can decide, for each filter stage, the right coefficients range. Note that
for a given biquad, the same range will be applied to the left and right (channel 1 and
channel 2).
Crossover biquad does not have the availability of this feature, maintaining the [-1;1) range
unchanged.
7.22
Miscellaneous registers (address 0x4B, 0x4C)
7.22.1
Rate power-down enable (RPDNEN) bit (address 0x4B, bit D7)
In the STA382BW, by default, the power-down pin and I2C power-down act on mute
commands to perform the fade-out. This default can be changed so that the fade-out can be
started using master volume. The RPDNEN bit, when set, activates this feature.
D7
D6
D5
D4
D3
D2
D1
D0
CEXT_B4[1]
CEXT_B4[0]
CEXT_B3[1]
CEXT_B3[0]
CEXT_B2[1]
CEXT_B2[0]
CEXT_B1[1]
CEXT_B1[0]
10
10
10
1
0
D7
D6
D5
D4
D3
D2
D1
D0
reserved
reserved
CEXT_B7[1]
CEXT_B7[0]
CEXT_B6[1]
CEXT_B6[0]
CEXT_B51]
CEXT_B5[0]
00
10
10
1
0
CEXT_Bx[1]
CEXT_Bx[0]
Range
00
[-1;1)
01
[-2;2)
10
[-4;4)
1
1
Reserved
D7
D6
D5
D4
D3
D2
D1
D0
RPDNEN
BRIDGOFF
CPWMEN
reserved
01
10
01
0
0
D7
D6
D5
D4
D3
D2
D1
D0
LPDP
LPD
LPDE
PNDLSL[2]
PNDLSL[1]
PNDLSL[0]
reserved
SHEN
01
00
11
0
0



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