STA382BW datasheet(149/172 Pages) STMICROELECTRONICS

149 / 172 page

STA382BW

Doc ID 022783 Rev 1

149/172

The output PLL frequency formula is:

where Fin is the input clock frequency from the pad.

Table 166.

PLL factors

PLL parameter

Min

Max

FRAC

65535

IDIV

NDIV

Table 167.

PLL register 0x43 bits

Bit

R/W

RST

Name

Description

7R/W

PLL_DITH(1:0)

‘00’:PLL clock dithering disabled

‘01’:PLL clock dithering enabled (triangular))

‘10’: PLL clock dithering enabled (rectangular)

‘11’: Reserved

6R/W

5R/W

NDIV

PLL loop divider

4R/W

3R/W

2R/W

1R/W

0R/W

Table 168.

PLL register 0x44 bits

Bit

R/W

RST

Name

Description

R/W

PLL_DPD

‘0’: any PLL dividers change is implemented via PLL

power-down

‘1’: PLL divider change will happen without PLL

power-down

R/W

PLL_FCT

‘0’:PLL use integer ratio

‘1’:PLL use fractional ratio

R/W

PLL_STB

PLL synchronous divider changes strobe

R/W

PLL_STBBYP

‘0’: PLL_STB is active

‘1’: PLL_STB control is bypassed

3R/W

PLL_IDIV (3:0)

Input PLL divider

2R/W

1R/W

0R/W

Fin

NDIV

()

IDIV

()

---------------------------

FRAC

65536

-----------------

⎝⎠

⎛⎞

⎝⎠

⎛⎞

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