CY8C53_11 datasheet(3/106 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 3 of 106

1. Architectural Overview

Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Figure 1-1 illustrates the major components of the CY8C53

family. They are:

ARM Cortex-M3 CPU subsystem

Nonvolatile subsystem

Programming, debug, and test subsystem

Inputs and outputs

Clocking

Power

Digital subsystem

Analog subsystem

PSoC’s

digital

subsystem

provides

half

its

unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast,

low-power UDBs. PSoC Creator provides a library of pre-built

and tested standard digital peripherals (UART, SPI, LIN, PRS,

CRC, timer, counter, PWM, AND, OR, and so on) that are

mapped to the UDB array. The designer can also easily create a

digital circuit using boolean primitives by means of graphical

design entry. Each UDB contains programmable array logic

(PAL)/programmable logic device (PLD) functionality, together

with a small state machine engine to support a wide variety of

peripherals.

Analog System

LCD Direct

Drive

CapSense

Temperature

Sensor

Opamp

ADC

2x DAC

2 x SC/ CT Blocks

(TIA, PGA, Mixer etc)

4 x

CMP

System Wide

Resources

Program

Debug

Trace

Program &

Debug

8051or

Cortex M3 CPU

Interrupt

Controller

PHUB

DMA

Cache

Controller

SRAM

FLASH

EEPROM

CPU System

Memory System

System Bus

Digital Interconnect

Analog Interconnect

1.8 to 3.6 V

( Optional )

425 MHz

(Optional)

Xtal

Osc

32.768 KHz

( Optional)

RTC

Timer

IMO

WDT

and

Wake

ILO

Clocking System

1.8 V LDO

SMP

POR and

LVD

Sleep

Power

Power Management

System

USB

PHY

3 per

Opamp

SAR

ADC

CAN

2.0

I2C

Master/

Slave

Universal Digital Block Array (24 x UDB)

4 x

Timer

Counter

PWM

FS USB

2.0

Digital System

UDB

UART

Logic

12- Bit PWM

I2C Slave

8- Bit SPI

12- Bit SPI

Logic

8- Bit

Timer

16- Bit PRS

UDB

8- Bit

Timer

Quadrature Decoder

16-Bit

PWM

UDB

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