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CY8C53 Fiches technique(PDF) 29 Page - Cypress Semiconductor

No de pièce CY8C53
Description  Programmable System-on-Chip (PSoC) DC to 67 MHz operation
PDF  106 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C53 Fiches technique(HTML) 29 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Document Number: 001-66237 Rev. *A
Page 29 of 106
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of
the eight drive modes listed in Table 6-6. Three configuration bits
are used for each pin (DM[2:0]) and set in the PRTxDM[2:0]
registers. Figure 6-11 depicts a simplified pin view based on
each of the eight drive modes. Table 6-6 shows the I/O pin’s drive
state based on the port data register value or digital array signal
if bypass mode is selected. Note that the actual I/O pin voltage
is determined by a combination of the selected drive mode and
the load at the pin. For example, if a GPIO pin is configured for
resistive pull-up mode and driven high while the pin is floating,
the voltage measured at the pin is a high logic state. If the same
GPIO pin is externally tied to ground then the voltage
unmeasured at the pin is a low logic state.
Figure 6-11. Drive Mode
High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Table 6-6. Drive Modes
Diagram
Drive Mode
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedence analog
0
0
0
High-Z
High-Z
1
High Impedance digital
0
0
1
High-Z
High-Z
2
Resistive pull-up[7]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[7]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High-Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High-Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[7]
1
1
1
Res High (5K)
Res Low (5K)
High Impedance
Analog
PS
DR
PS
DR
PS
DR
0.
High Impedance
Digital
1.
Resistive
Pull-Up
2.
Resistive
Pull-Down
3.
Open Drain,
Drives Low
4.
Open Drain,
Drives High
5.
Strong Drive
6.
Resistive
Pull-Up and Pull-Down
7.
Vddio
Pin
Pin
Pin
Vddio
Pin
Pin
Pin
Pin
Pin
PS
DR
PS
DR
PS
DR
PS
DR
PS
DR
Vddio
Vddio
Vddio
Note
7. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
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