CY8C53_11 datasheet(53/106 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 53 of 106

Figure 8-10. DAC Block Diagram

8.9.1 Current DAC

The current DAC (IDAC) can be configured for the ranges 0 to

32 µA, 0 to 256 µA, and 0 to 2.04 mA. The IDAC can be

configured to source or sink current.

8.9.2 Voltage DAC

For the voltage DAC (VDAC), the current DAC output is routed

through resistors. The two ranges available for the VDAC are 0

to 1.024 V and 0 to 4.096 V. In voltage mode any load connected

to the output of a DAC should be purely capacitive (the output of

the VDAC is not buffered).

8.10 Up/Down Mixer

In continuous time mode, the SC/CT block components are used

to build an up or down mixer. Any mixing application contains an

input signal frequency and a local oscillator frequency. The

polarity of the clock, Fclk, switches the amplifier between

inverting or noninverting gain. The output is the product of the

input and the switching function from the local oscillator, with

frequency components at the local oscillator plus and minus the

signal frequency (Fclk + Fin and Fclk - Fin) and reduced-level

frequency components at odd integer multiples of the local

oscillator frequency. The local oscillator frequency is provided by

the selected clock source for the mixer.

Continuous time up and down mixing works for applications with

input signals and local oscillator frequencies up to 1 MHz.

Figure 8-11. Mixer Configuration

Reference

Source

Scaler

I source Range

1x , 8x , 64x

I sink Range

1x , 8x , 64x

Vout

Iout

Vref

Vout

mix 0 20 k or 40 k

sc_clk

Vin

C2 = 1.7 pF

C1 = 850 fF

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