SH7708 datasheet(452/633 Pages) RENESAS

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434

16.3.1

Clock Timing

Table 16.5

Clock Timing (VCC = 3.3 ± 0.3 V, Ta = –20 to +75°C, Maximum External Bus

Operating Frequency: 15 MHz)

Item

Symbol

Min

Max

Unit

Figure

EXTAL clock input frequency

fEX

MHz

16.1

EXTAL clock input cycle time

tEXcyc

33.3

500

EXTAL clock input low level pulse width

tEXL

8*1 or 12*2

—ns

EXTAL clock input high level pulse width

tEXH

8*1 or 12*2

—ns

EXTAL clock input rise time

tEXr

—4

EXTAL clock input fall time

tEXf

—4

CKIO clock frequency (input)

fCKI

MHz

16.2

CKIO clock cycle time (input)

tCKIcyc

66.7

125

CKIO clock low-level pulse width (input)

tCKIL

8—

CKIO clock high-level pulse width (input)

tCKIH

8—

CKIO clock rise time (input)

tCKIr

—4

CKIO clock fall time (input)

tCKIf

—4

CKIO clock output frequency (output)

fOP

MHz

16.3

CKIO clock cycle time (output)

tcyc

66.7

1000

CKIO clock low-level pulse width (output)

tCKOL

—

CKIO clock high-level pulse width (output)

tCKOH

—

CKIO clock rise time (output)

tCKOr

—7

CKIO clock fall time (output)

tCKOf

—7

Power-on oscillation settling time

tOSC1

—

16.4

Power-on oscillation settling time/mode

setting

tOSCMD

—

BREQ reset hold time

tBREQRH

0—

RESET set-up time

tRESS

—

BREQ set-up time

tBREQS

—

MD reset hold time

tMDRH

—

Reset assert time

tRESW

—

tcyc

16.4,

16.5,

16.11

Standby return oscillation settling time 1

tOSC2

—

16.5

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