SH7708 datasheet(398/633 Pages) RENESAS

398 / 633 page

380

Figure 13.11 shows SCI transmission with the multiprocessor format.

TDRE

TEND

TXI interrupt

request

TXI interrupt

request

TEI interrupt

request

TXI interrupt

handler writes

data to TDR and

clears TDRE bit

to 0

1 frame

0/1

Multi-

processor

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

(mark)

state

0/1

Multi-

processor

bit

Figure 13.11 SCI Multiprocessor Transmit Operation (Example: 8-Bit Data with

Multiprocessor Bit and One Stop Bit)

Receiving Multiprocessor Serial Data: Figure 13.12 shows a sample flowchart for receiving

multiprocessor serial data. The procedure for receiving multiprocessor serial data is:

1. ID receive cycle: Set the MPIE bit in the serial control register (SCSCR) to 1.

2. SCI status check and compare to ID reception: Read the serial status register (SCSSR), check

that RDRF is set to 1, then read data from the receive data register (SCRDR) and compare with

the processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and

clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0.

3. SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data

from the receive data register (SCRDR).

4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER

bits in SCSSR to identify the error. After executing the necessary error handling, clear both

ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a

framing error occurs, the RxD pin can be read to detect the break state.

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