M36DR232B datasheet(17/46 Pages) STMICROELECTRONICS

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M36D232A, M36DR232B

Table 17. Status Register Bits (1)

Note: 1. Logic level '1' is High, '0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

2. In case of double word program DQ7 refers to the last word input.

Name

Logic Level

Definition

Note

Data

Polling

'1'

Erase Complete or erase block

in Erase Suspend.

Indicates the P/E.C. status, check

during Program or Erase, and on

completion before checking bits DQ5

for Program or Erase Success.

'0'

Erase On-going

Program Complete or data of

non erase block during Erase

Suspend.

Program On-going (2)

Toggle Bit

'-1-0-1-0-1-0-1-'

Erase or Program On-going

Successive reads output

complementary data on DQ6 while

Programming or Erase operations are

on-going. DQ6 remains at constant

level when P/E.C. operations are

completed or Erase Suspend is

acknowledged.

Program Complete

'-1-1-1-1-1-1-1-'

Erase Complete or Erase

Suspend on currently addressed

block

Error Bit

'1'

Program or Erase Error

This bit is set to '1' in the case of

Programming or Erase failure.

'0'

Program or Erase On-going

Reserved

Erase Time

Bit

'1'

Erase Timeout Period Expired

P/E.C. Erase operation has started.

Only possible command entry is Erase

Suspend (ES)

'0'

Erase Timeout Period On-going

An additional block to be erased in

parallel can be entered to the P/E.C:

Toggle Bit

'-1-0-1-0-1-0-1-'

Erase Suspend read in the

Erase Suspended Block.

Erase Error due to the currently

addressed block (when DQ5 =

'1').

Indicates the erase status and allows

to identify the erased block.

Program on-going or Erase

Complete.

Erase Suspend read on non

Erase Suspend block.

Reserved

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