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L99PM72PXP Fiches technique(PDF) 80 Page - STMicroelectronics

No de pièce L99PM72PXP
Description  Advanced power management system IC with embedded LIN and high speed CAN transceiver supporting CAN Partial Networking
PDF  128 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99PM72PXP Fiches technique(HTML) 80 Page - STMicroelectronics

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Doc ID 023553 Rev 3
OC0, OC1: operating code (00 for ‘write’ mode)
A0 to A5: address bits
An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).
The device enters a Fail-Safe state.
6.1.7
Format of data shifted out at SDO during Write cycle
Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte(s) represent(s) the previous content of the accessed register
Table 50.
Write command format: data byte 1
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Table 51.
Write command format: data byte 2
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Table 52.
Format of data shifted out at SDO during write cycle: global status
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Communication
error
Not (chip reset
or comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Table 53.
Format of data shifted out at SDO during write cycle: data byte 1
MSB
Previous content of addressed register
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Table 54.
Format of data shifted out at SDO during write cycle: data byte 2
MSB
Previous content of addressed register
LSB
D7
D6
D5
D4
D3
D2
D1
D0



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