UPD17062 datasheet(117/298 Pages) RENESAS

117 / 298 page

115

µPD17062

Fig. 11-3

Interrupt Acceptance Timing Chart

(2) When two or more interrupts (e.g., rising edge at the INTNC pin and falling edge at the VSYNC pin) are used

(a) Hardware priorities

(b) Software priorities

Instruction

MOV

WR, #0101B

POKE

INTPM, WR

INTE

INTNC pin

IRQVSYN flag

IPNC flag

IPVSYN flag

IRQNC flag

VSYNC pin

Interrupt

cycle

Interrupt

cycle

VSYNC pin interrupt acceptance

INTNC pin interrupt holding period

INTNC pin interrupt processing

VSYNC pin

interrupt processing

VSYNC pin interrupt holding period

INTNC pin interrupt acceptance

Instruction

MOV

WR, #0100B

POKE

INTPM, WR

INTE

INTNC pin

IRQNC flag

IPNC flag

IPVSYN flag

IRQNC flag

VSYNC pin

MOV

WR, #0101B

POKE

INTPM, WR

INTNC pin interrupt holding period

VSYNC pin interrupt acceptance

INTNC pin interrupt

processing

INTNC pin interrupt acceptance

VSYNC pin interrupt holding period

VSYNC pin interrupt processing

Interrupt

cycle

Interrupt

cycle

UPD17062 Fiches technique(PDF) 117 Page - Renesas Technology Corp

UPD17062 Fiches technique(HTML) 117 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL