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tPD

OUTx Low

OUTx High

OUTx

Time

10%

INx

Figure 8-13. Propagation Delay

8.3.9 Pin Diagrams

This section presents the I/O structure of all digital input and output pins.

8.3.9.1 Logic Level Input Pin (Internal Pulldown)

Figure 8-14 shows the input structure for the logic levels pins INHx, INLx, nSLEEP, SCLK and SDI. The input

can be driven with an external resistor to GND or an external logic voltage supply. It is recommended to pull

these pins low in device sleep mode to reduce leakage current through the internal pull-down resistors.

AVDD

Logic High

INPUT

VIH

STATE

Tied to AVDD

CONNECTION

VIL

Tied to GND

Logic Low

RPD

ESD

Figure 8-14. Logic-Level Input Pin Structure

8.3.9.2 Logic Level Input Pin (Internal Pullup)

Figure 8-15 shows the input structure for the logic level pin nSCS. The input can be driven with an external

resistor to GND or an external logic voltage supply .

AVDD

Logic High

INPUT

VIH

STATE

Tied to AVDD

CONNECTION

VIL

Tied to GND

Logic Low

AVDD

ESD

RPU

Figure 8-15. nSCS Input Pin Structure

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DRV8317

SLVSGT3 – DECEMBER 2022

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